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| PRELIMINARY CY2544 CY2546 Quad PLL Programmable Clock Generator with Spread Spectrum Features * Four fully integrated phase-locked loops (PLLs) * Input Frequency range: -- External crystal: 8 to 48 MHz -- External reference: 8 to 166 MHz clock * Wide operating output frequency range -- 3 to 166 MHz * Programmable Spread Spectrum with Center and Down Spread option and Lexmark modulation profile * Two VDD core voltage options: -- 2.5V, 3.0V, and 3.3V for CY2544 -- 1.8V for CY2546 * Selectable output voltages: -- 2.5V, 3.0V, and 3.3V for CY2544 * * * * * * * -- 1.8V for CY2546 Frequency Select feature with option to select eight different frequencies Low jitter, high accuracy outputs Up to nine clock outputs Programmable output drive strength Glitch-free outputs while frequency switching 24-pin QFN package Commercial and Industrial temperature ranges Benefits * Multiple high-performance PLLs allow synthesis of unrelated frequencies * Nonvolatile programming for customized PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies * Two Spread Spectrum capable PLLs with Linear or Lexmark profile for maximum EMI reduction * Spread Spectrum PLLs can be disabled or enabled separately * PLLs can be programmed for system frequency margin tests * Meets critical timing requirements in complex system designs * Suitable for PC, consumer, and networking applications * Ability to synthesize standard frequencies with ease * Application compatibility in standard and low-power systems Block Diagram EXCLKIN 4 of 6 Crossbar Switch XIN XOUT OSC PLL1 Output Dividers and Bank 2 CLK1 Bank 1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 FS0 FS1 FS2 MUX and Control Logic PLL2 Drive Strength Control Bank 3 CLK8 CLK9 PLL3 (SS) PLL4 (SS) SSON PD#/OE Cypress Semiconductor Corporation Document #: 001-12563 Rev. *A * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised February 28, 2007 [+] Feedback PRELIMINARY CY2544 CY2546 Pin Configuration VDD_CORE EXCLKIN XOUT EXCLKIN XOUT CLK9 CLK9 20 GND VDD 24 23 22 21 20 19 24 XIN 23 22 21 GND CLK1 VDD_CLK_B1 PD#OE 1 18 GND CLK8 VDD_CLK_B3 GND 19 XIN GND CLK1 VDD_CLK_B1 PD#OE 1 18 GND CLK8 VDD_CLK_B3 2 17 2 17 3 CY2544 24LD QFN 16 3 CY2546 24LD QFN 16 4 15 CLK7/SSON VDD_CLK_B2 4 15 CLK7/SSON VDD_CLK_B2 NC CLK2 5 14 VDD_CORE CLK2 5 14 6 13 CLK6 6 13 CLK6 7 8 9 10 11 12 7 8 9 10 11 12 PD#/OE/FS1 CLK5 CLK3/FS0 CLK4/FS2 GND GND PD#/OE/FS1 CLK5 CLK3/FS0 Pin Description - CY2544 (2.5V, 3.0V or 3.3V VDD) Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND CLK1 VDD_CLK_B1 PD#/OE NC CLK2 GND CLK3/FS0 PD#/OE/FS1 CLK4/FS2 CLK5 GND CLK6 VDD_CLK_B2 CLK7/SSON VDD_CLK_B3 CLK8 GND Name Power Output Power Input NC Output Power Output/Input Input Output/Input Output Power Output Power Output/Input Power Output Power I/O Description Power Supply Ground for Core Programmable Output Clock 2.5V/3.0V/3.3V Power Supply for Output Bank1 (CLK1, CLK2, CLK3) output Power Down or Output Enable No Connect Programmable Output Clock Power Supply Ground for Output Bank 1 Multifunction Programmable pin,CLK3 Output Clock or Frequency Select pin FS0 Multifunction Programmable pin, Power Down, Output Enable or Frequency Select pin FS1 Multifunction Programmable pin, CLK4 Output or Frequency Select input pin FS2 Programmable Output Clock Power Supply Ground for Output Bank 2 Programmable Output Clock 2.5V/3.0V/3.3V Power Supply for Output Bank2 (CLK4, CLK5, CLK6) output Multifunction Programmable pin, CLK7 Output or SSON input 2.5V/3.0V/3.3V Power Supply for Output Bank3 (CLK7, CLK8, CLK9) output Programmable Output Clock Power Supply Ground for Output Bank 3 Document #: 001-12563 Rev. *A CLK4/FS2 GND GND Page 2 of 11 [+] Feedback PRELIMINARY Pin Description - CY2544 (2.5V, 3.0V or 3.3V VDD) (continued) Pin Number 19 20 21 22 23 24 GND CLK9 EXCLKIN VDD XOUT XIN Name Power Output Input Power Output Input I/O Description Power Supply Ground for Core Programmable Output Clock External Clock Input 2.5V/3.0V/3.3V Power Supply CY2544 CY2546 Crystal Output Crystal Input Pin Description - CY2546 (1.8V VDD_CORE) Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GND CLK1 VDD_CLK_B1 PD#/OE VDD_CORE CLK2 GND CLK3/FS0 PD#/OE/FS1 CLK4/FS2 CLK5 GND CLK6 VDD_CLK_B2 CLK7/SSON VDD_CLK_B3 CLK8 GND GND CLK9 EXCLKIN VDD_CORE XOUT XIN Name Power Output Power Input Power Supply Output Power Output/Input Input Output/Input Output Power Output Power Output/Input Power Output Power Power Output Input Power Output Input I/O Description Power Supply Ground for Core Programmable Output Clock 1.8V Power Supply for Output Bank1 (CLK1, CLK2, CLK3) output Power Down or Output Enable 1.8V Power Supply for Core Programmable Output Clock Power Supply Ground For Output Bank 1 Multifunction Programmable pin,CLK3 Output Clock or Frequency Select pin FS0 Multifunction Programmable pin, Power Down, Output Enable or Frequency Select pin FS1 Multifunction Programmable pin, CLK4 Output or Frequency Select input pin FS2 Programmable Output Clock Power Supply Ground for Output Bank 2 Programmable Output Clock 1.8V Power Supply for Output Bank2 (CLK4, CLK5, CLK6) output Multifunction Programmable pin, CLK4 Output or SSON input 1.8V Power Supply for Output Bank3 (CLK7, CLK8, CLK9) output Programmable Output Clock Power Supply Ground for Output Bank 3 Power Supply Ground for Core Programmable Output Clock External Low Voltage Reference Clock Input 1.8V Power Supply for Core Crystal Output Crystal Input Document #: 001-12563 Rev. *A Page 3 of 11 [+] Feedback PRELIMINARY General Description The CY2544 and CY2546 are four-PLL programmable Spread Spectrum Clock Generators used to reduce EMI found in high-speed digital electronic systems. Two of the four PLLs have Spread Spectrum capability. The spread spectrum feature is turned on or off using the control pin SSON. The advantage of having four PLLs is that a single device can generate up to four independent families of frequencies from a single crystal or reference input frequency. Generally, a design requires up to four oscillators to achieve the same result as a single CY2544 or CY2546. The device uses Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. Frequency modulating the clock greatly reduces the measured EMI at the fundamental and harmonic frequencies. This reduction in radiated energy significantly reduces the cost of complying with regulatory agency (EMC) requirements and improves time-to-market without degrading the system performance. The CY2544 and CY2546 use a factory/field-programmable configuration memory array to provide customization for output frequencies, frequency select options, spread characteristics like spread percentage and modulation frequency, output drive strength and crystal load capacitance. Customized devices are configured using CyberClocksTM software or by contacting the factory. The spread percentage is programmed to either center spread or down spread with various spread percentages. The range for center spread is from 0.125% to 2.50%. The range for down spread is from -0.25% to -5.0%. Contact the factory for smaller or larger spread percentage amounts, if required. CY2544 CY2546 The input to the CY2544 and CY2546 is either a crystal or a clock signal. The input frequency range for crystals is 8 MHz to 48 MHz, and for clock signals is 8 MHz to 166 MHz. In addition, there is a separate input for a clock reference. The CY2544 and CY2546 have nine clock outputs and each output has four possible input sources. There are three frequency select lines FS(2:0) that provide an option to select eight different sets of frequencies among each of the four PLLs. Each output has programmable output divider options. Output 1 has eight possible divider values and outputs 2-9 have four possible divider values for maximum flexibility. The 2-bit or 3-bit output dividers are programmable, providing a wide output frequency range. The outputs are glitch-free when frequency is switched using output dividers. The outputs can have a predictable phase relationship, if the clock source is the same PLL and divider values are 2, 3, 4, or 6. The output banking feature allows the three sets of frequencies to operate at three different voltages. Selectable output voltage options are 2.5V, 3.0V, or 3.3V for CY2544 and 1.8V for CY2546 part. The CY2544 and CY2546 are available in 24-pin QFN packages with commercial and industrial operating temperature ranges. Table 1. Supply Voltage Options Device CY2544 CY2546 VDD Supply Voltage 2.5V, 3.0V or 3.3V 1.8V Document #: 001-12563 Rev. *A Page 4 of 11 [+] Feedback PRELIMINARY CY2544 CY2546 Absolute Maximum Conditions Parameter VDD VDD_CORE Description Supply Voltage for CY2544 Supply Voltage for CY2546 Condition Min. -0.5 -0.5 Max. 4.5 2.6 Unit V V VDD_CLK_BX VIN TS ESDHBM UL-94 MSL Supply Voltage for CY2544 Supply Voltage for CY2546 Input Voltage Temperature, Storage Flammability Rating Moisture Sensitivity Level Relative to VSS Non Functional @1/8 in. QFN package -0.5 -0.5 -0.5 -65 2000 V-0 4.5 2.6 +150 V V C Volts VDD + 0.5 VDC ESD Protection (Human Body Model) MIL-STD-883, Method 3015 - 3 Recommended Operating Conditions Parameter VDD VDD VDD VDD Operating at 3.3V for CY2544 VDD Operating at 3.0V for CY2544 VDD Operating at 2.5V for CY2544 Description Min. 3.00 2.70 2.25 Typ. - - - Max. Unit 3.60 3.30 2.75 V V V VDD_CORE VDD_CLK_BX VDD_CLK_BX VDD_CLK_BX VDD_CLK_BX TAC TAI CLOAD tPU VDD_CORE Operating at 1.8V for CY2546 Output Driver Voltage for Bank 1, 2 and 3 Operating at 3.3V (CY2544) Output Driver Voltage for Bank 1, 2 and 3 Operating at 3.0V (CY2544) Output Driver Voltage for Bank 1, 2 and 3 Operating at 2.5V (CY2544) Output Driver Voltage for Bank 1, 2 and 3 Operating at 1.8V (CY2546) Commercial Ambient Temperature Industrial Ambient Temperature Maximum Load Capacitance Power-up time for all VDD pins to reach minimum specified voltage (power ramps must be monotonic) 1.65 3.00 2.70 2.25 1.65 0 -40 - 0.05 - - - - - - - - - 1.95 3.60 3.30 2.75 1.95 +70 +85 15 500 V V V V V C C pF ms DC Electrical Specifications Parameter VOL VOH VIL VIH VILX VIHX Description Output Low Voltage, All CLK pins Output High Voltage, All CLK pins All Inputs except XIN All Inputs except XIN Input Low Voltage, clock input to XIN pin Input High Voltage, clock input to XIN pin Conditions All VDD levels, IOL = 8 mA All VDD levels, IOH = -8 mA All VDD levels All VDD levels All VDD levels All VDD levels Min. - VDD - 0.4 -0.3 0.8 * VDD -0.3 1.44 - - - - - - - Typ. - - - - - - - - - - 15 50 - Max. 0.4 - 0.2 * VDD VDD + 0.3 0.36 2.0 1 1 1 25 - - 7 Unit V V V V V V A A A A mA A pF IILPDOE IIHPDOE IILSR IIHSR IDD[1] IDDS CIN Input Low Current, PD#/OE and FS0,1,2 pins VIN = VSS (No Internal pull up) Input High Current, PD#/OE and FS0,1,2 pins VIN = VDD (No Internal pull up) Input Low Current, SSON pin Input High Current, SSON pin Supply Current Standby Current Input Capacitance - All inputs except XIN VIN = VSS (Internal pull down = 160k typical) VIN = VDD (Internal pull down = 160k typical) All clocks running, No load All output power down SSON, OE, PD# or FS inputs Document #: 001-12563 Rev. *A Page 5 of 11 [+] Feedback PRELIMINARY CY2544 CY2546 AC Electrical Specifications Parameter FIN (crystal) FIN (clock) FOUT DC Description Crystal Frequency Input Clock Frequency (XIN or EXCLKIN) Output Clock Frequency Conditions Min. 8 8 3 45 Typ. Max. Unit - - - 50 48 166 166 55 MHz MHz MHz % Output Duty Cycle All Clocks except Ref Out Duty Cycle is defined in Figure 2, "Duty Cycle Definition," on page 8; t1/t2, 50% of VDD Ref Out Duty Cycle Ref In Min 45%, Max 55% DC 40 0.8 0.8 - - - - 60 - - - % V/ns V/ns ps ER EF TCCJ1 CLK1-9 Rising Edge Rate CLK1-9 Falling Edge Rate Cycle-to-cycle Jitter VDD = All, 20% to 80% VDD VDD = All, 20% to 80% VDD Configuration dependent. See Table 2, "Configuration Example for Jitter," on page 6 Configuration dependent. See Table 2, "Configuration Example for Jitter," on page 6 TLTJ Long Term Jitter (1000 cycle period jitter) PLL Lock Time - - - ns T10 - 1 3 ms Table 2. Configuration Example for Jitter Reference Description Max Jitter (ps) on Output 1(48MHz) 155 135 770 535 Max Jitter (ps) on Output 2 (27 MHz) 255 225 580 575 Max Jitter (ps) on Max Jitter (ps) on Output 3 (166 MHz) Output 4 (74.25 MHz) 170 100 630 520 195 125 1105 795 Cycle-to-Cycle Jitter 27MHz 48 MHz 27MHz 48 MHz TCCJ1 TCCJ1 TLTJ TLTJ Long Term Jitter Note 1. Configuration dependent. Document #: 001-12563 Rev. *A Page 6 of 11 [+] Feedback PRELIMINARY CY2544 CY2546 Recommended Crystal Specification for SMD Package Parameter Fmin Fmax R1(max) C0(max) CL(max) DL(max) Minimum Frequency Maximum Frequency Maximum Motional Resistance (ESR) Maximum Shunt Capacitance Maximum Parallel Load Capacitance Maximum Crystal Drive Level Description Range 1 Range 2 Range 3 8 14 135 4 18 300 14 28 50 4 14 300 28 48 30 2 12 300 Unit MHz MHz pF pF W Recommended Crystal Specification for Thru-Hole Package Parameter Fmin Fmax R1(max) C0(max) CL(max) DL(max) Minimum Frequency Maximum Frequency Maximum Motional Resistance (ESR) Maximum Shunt Capacitance Maximum Parallel Load Capacitance Maximum Crystal Drive Level Description Range 1 Range 2 Range 3 8 14 90 7 18 1000 14 24 50 7 12 1000 24 32 30 7 12 1000 Unit MHz MHz pF pF W Document #: 001-12563 Rev. *A Page 7 of 11 [+] Feedback PRELIMINARY Test and Measurement Setup Figure 1. Test and Measurement Setup V DDs 0.1 F DUT Outputs C LOAD CY2544 CY2546 GND Voltage and Timing Definitions Figure 2. Duty Cycle Definition t1 t2 VDD 50% of VDD Clock Output 0V Figure 3. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 t3 t4 V DD 80% of VDD 20% of VDD 0V Clock Output Document #: 001-12563 Rev. *A Page 8 of 11 [+] Feedback PRELIMINARY Ordering Information Part Number[2] Lead-free CY2544CXXX CY2544CXXXT CY2544FC CY2544FCT CY2546Cxxx CY2546CxxxT CY2546FC CY2546FCT CY2544IxxxT CY2544FI CY2544FIT CY2546Ixxx CY2546IxxxT CY2546FI CY2546FIT 24-pin QFN 24-pin QFN -Tape & Reel 24-pin QFN 24-pin QFN - Tape & Reel 24-pin QFN 24-pin QFN -Tape & Reel 24-pin QFN 24-pin QFN -Tape & Reel 24-pin QFN -Tape & Reel 24-pin QFN 24-pin QFN - Tape & Reel 24-pin QFN 24-pin QFN -Tape & Reel 24-pin QFN 24-pin QFN -Tape & Reel 3.3, 3.0 or 2.5 3.3, 3.0 or 2.5 3.3, 3.0 or 2.5 3.3, 3.0 or 2.5 1.8 1.8 1.8 1.8 3.3, 3.0 or 2.5 3.3, 3.0 or 2.5 3.3, 3.0 or 2.5 1.8 1.8 1.8 1.8 Type VDD(V) CY2544 CY2546 Temperature Range Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40C to +85C Industrial, -40C to +85C Industrial, -40C to +85C Industrial, -40C to +85C Industrial, -40C to +85C Industrial, -40C to +85C Industrial, -40C to +85C Note 2. xxx Indicates Factory Programmable are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative. F in the part number indicates field programmable using CyberClocks Online software. Document #: 001-12563 Rev. *A Page 9 of 11 [+] Feedback PRELIMINARY Package Drawing and Dimensions Figure 4. 24-Lead QFN 4x4 mm (Subcon Punch Type Pkg with 2.49x2.49 EPAD) LF24A SIDE VIEW TOP VIEW 0.05 3.90 4.10 ?0.50 N 1 2 2.45 2.55 3.70 3.80 3.90 4.10 2.49 SOLDERABLE EXPOSED PAD CY2544 CY2546 BOTTOM VIEW C 0.230.05 2.49 0.20 REF. N 1 2 0.45 PIN1 ID 0.20 R. 1.00 MAX. 0.05 MAX. 0.80 MAX. 3.70 3.80 0.30-0.50 0-12 C SEATING PLANE 0.420.18 (4X) 2.45 2.55 0.50 NOTES: 1. HATCH IS SOLDERABLE EXPOSED METAL. 51-85203-*A 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.042g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE PART # LF24A LY24A DESCRIPTION STANDARD LEAD FREE CyberClocks is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-12563 Rev. *A Page 10 of 11 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback PRELIMINARY CY2544 CY2546 Document History Page Document Title: CY2544/CY2546 Quad PLL Programmable Clock Generator with Spread Spectrum Document Number: 001-12563 REV. ** *A ECN NO. 690257 790516 Issue Date See ECN See ECN Orig. of Change RGL RGL New Data Sheet Separated the Pin Configuration drawing into two to show the difference between CY2544 and CY2546 pin outs. Changed the IDD from 22mA maximum to 25mA typical Changed IILSR Internal pull down from 100K to 160K Changed IIHSR Internal pull down from 100k to 160K and changed the maximum value from 10A to 25A Changed IILPDOE to No Internal pull up and changed the maximum value from 10A to 1A Changed IIHPDOE to no Internal pull up Description of Change Document #: 001-12563 Rev. *A Page 11 of 11 [+] Feedback |
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